1. Field of the Invention
This invention relates to a latch circuit and more particularly to a high performance latching circuit that is logically hazard-free and advantageously implemented in semiconductor integrated circuit technology.
2. Description of the Prior Art
Clocked latching circuits are well known in the art as bistable circuits having both clock signal and data signal inputs wherein the output is not altered from its bistable state until the occurrence of a clock signal at the input. Latch circuits utilizing a combination of logic elements such as "OR" and "AND" logic circuitry are well known. Generally, this class of circuits includes a feedback path from the output, to thereby latch the output node to its desired logic state.
It is desirable to improve the performance of latch circuits with respect to switching time, signal response, number of circuit elements required, reliability of operation, and versatility in terms of data and clock signal inputs, thereby to increase the flexibility, versatility, and capability of data processing systems. Another advantageous property of latching circuits is to avoid race conditions and "glitches" by providing circuits that are logically hazard free.
Moreover, a circuit should be readily integratable in monolithic semiconductor circuit technology. To this end, it is desired to utilize minimum semiconductor space to perform a latching function and to dissipate minimum power. A latch circuit should also be compatible with the circuit family technology used for related circuits.